1. Technical Field
The present invention relates to semiconductor manufacturing and, in particular, to testing of semiconductor devices. Still more particularly, the present invention provides a defect monitor for semiconductor manufacturing capable of performing analog resistance measurements.
2. Description of Related Art
Bringing up a new semiconductor can be challenging and requires a variety of yield monitors to determine the health of the process and to find systematic problems. Several known structures, such as long wires, minimum spaced wires, and via chains are used to determine back end of line health. Back end of line (BEOL) includes wires and vias. Front end of line (FEOL) includes transistors and other devices. Wires may appear in metal layers or in the semiconductor itself. Vias are used to connect metal layers to other metal layers or to portions of the semiconductor device.
When a long wire is fabricated, a defect may occur where the wire is open at a point in the circuit. Similarly, a via chain may be defective if the via chain is left open. On the other hand, minimum spaced wires may exist in a semiconductor device. If these wires are shorted, then the structures are defective.
To find random defects, one must isolate defects to a small area so failure analysis can study the defect. The surrounding support logic for the BEOL structures must be capable of isolating the failure. However, isolating defects in the BEOL structures has proven to be difficult and unreliable.